1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to memories within data processing systems and the adaptive control of comparisons performed with data stored in such memories.
2. Description of the Prior Art
Some memory associated with a processor consumes a significant proportion of the power consumption of that processor and memory combination. As an example, a processor core with a level one cache may have half of its power consumption associated with the level one cache. Perhaps 40% of the level one cache power consumption associated with cache TAG lookup operations. As the number of cache ways increases, the cache tag lookup consumption becomes greater. Such cache memories are desirable to achieve high performance operation and typically employ large fast and power hungry transistors and other circuit elements. It is also desirable to have a high capacity cache memory and these tend to be associated with high capacitance bit lines, which in turn increase our consumption.
As mentioned above, cache TAG lookup accounts for a significant proportion of cache memory power consumption. It has been recognised that in many circumstances, particularly in the embedded device market segment, the memory footprint (i.e. range of memory locations accessed) is frequently significantly less than the processor's address range. This is also a characteristic of high-end applications where wide 64-bit address space is provided, with relatively little of this address space in practise being used.
“TAG Overflow Buffering: An Energy-Efficient Cache Architecture” by Mirko Loghi, Paolo Azzoni and Massimo Poncino discloses a scheme in which an application program is profiled to determine the gross locality of the code concerned. The cache memory is then designed with a TAG width depending upon the profile results. A special register (the TAG Overflow Buffer (TOB)), is programmed with the current locality by the processor. Transfers that are within this region of memory are cached. Transfers from outside this region are not cached. This scheme requires that the cache be designed for a particular application (that is known in advance) and that software be written with the ability to update the TOB this scheme also results in lower performance (and higher power consumption) for transactions which fall outside the TOB region.
“Data Cache Energy Minimisation Through Programmable TAG Size Matching to the Applications” by Peter Petrov and Alex Orailoglu discloses a scheme in which the TAG length for a particular section of code is determined. This value is programmed into a register by a processor before the said section of code concern is executed. The scheme uses a special RAM array where bit lines can be disabled depending upon the value programmed into the register. This scheme requires the code to be analysed in advance and additional instructions to be written to program the TAG width (limiting where the scheme can be used). This scheme also reduces the processor performance due to the additional instructions that must be executed.
It will be appreciated that whilst the above schemes can exploit the address locality associated with many real life patterns of memory accesses, they suffer from the disadvantage that the application programs concerned must be modified to control the hardware in an appropriate manner for the application program concerned. This represents an additional burden to the programmer and means that the techniques cannot be used with existing legacy code.